FIG. 1a shows a cross section view of a conventional stacked-gate non-volatile memory cell 100 at an intermediate processing stage. Cell 100 has a polysilicon (gate) stack which includes floating gate 106 and control gate 110 insulated from each other by a composite oxide-nitride-oxide (ONO) dielectric layer 108. A tungsten layer (WSix) 112 overlies control gate 110. Floating gate 106 is insulated from the underlying silicon substrate 102 by a tunnel oxide layer 104. FIG. 1b shows a cross section view of cell 100 after formation of: (a) oxide spacers 116-a, 116-b along sidewalls of the gate stack, and (b) source region 114-a and drain region 114-b in substrate 102.
A simplified conventional process sequence to form memory cell 100 includes: forming tunnel oxide layer over substrate 102; depositing a first layer polysilicon over the tunnel oxide layer; forming an interpoly composite ONO dielectric layer over the first layer polysilicon; depositing a second layer polysilicon over the ONO dielectric; forming a tungsten silicide layer over the second layer polysilicon; and self-aligned mask and self-aligned etch (SAE) to form the gate stack as shown in FIG. 1a. In modern technologies, the control gate is often formed simultaneously with the gates of peripheral (CMOS) transistors, followed by cell self-aligned etch (SAE) of the first layer polysilicon and the ONO dielectric using the control gate as a mask. After formation of the gate stack, in some processes, polysilicon re-oxidation is performed. DDD mask and implant steps are then carried out to form the cell source DDD region (if for example a source DDD region is employed) and DDD regions for peripheral high voltage (HV) NMOS and PMOS transistors. Next, cell source/drain mask and implant steps are carried out to form cell source and drain regions 114-a, 114-b, followed by oxidation and anneal cycles. LDD mask and implant steps may then be carried out to form LDD junctions for the low voltage (LV) NMOS and PMOS transistors. Spacers (e.g., spacers 16-a, 116-b in FIG. 1b) are then formed along sidewalls of the gate stack in the cell and along the side-walls of the gates of the periphery transistors. This is followed by N+ and P+ mask and implant steps to complete the junction formation of the peripheral transistors.
The first and second polysilicon layers are deposited by means of Chemical Vapor Deposition (CVD). Both first and second polysilicon layers are in-situ doped (usually by phosphorus P31) to a relatively high level (e.g., 2xc3x971019 to 5xc3x971020 cmxe2x88x923). The level of polysilicon doping is usually controlled by gas flow rate and pressure of the gas compound containing P31, such as PH3. An example of a set of parameters associated with the polysilicon deposition of a conventional process is provided below.
There are a number of reasons for the high polysilicon doping. First, the high doping prevents or minimizes polysilicon depletion when gate bias is applied to the control gate of the memory cell or to the gate of the MOS transistor. Polysilicon depletion decreases gate capacitance thus reducing gate control in a MOS transistor channel region, and impairs other transistor/cell electrical characteristics. Second, the high doping helps maintain a proper value of polysilicon work function which impacts such important transistor/cell parameters as the threshold voltage. Third, the high doping reduces the world line resistance in the memory array, thus improving the memory performance. Fourth, the high doping reduces time delay associated with the peripheral transistor gate capacitance and resistance.
However, there are also drawbacks to the high polysilicon doping. The high doping leads to higher oxidation rate of polysilicon crystals. Higher oxidation rate in turn leads to a more pronounced xe2x80x9csmilingxe2x80x9d effect, i.e., an increased gate oxide thickness at the edges of the gate in MOS transistors, and similar increase of tunnel oxide thickness and ONO dielectric at the edges of the cell gate stack as shown in FIG. 1b by circles marked by reference numerals 118 and 120. Although some minimal xe2x80x9csmilingxe2x80x9d effect can serve a useful reliability purpose by rounding corners of polysilicon thus reducing the electric field peak at polysilicon edges, excessive xe2x80x9csmilingxe2x80x9d effect impairs gate control of the channel and the drive current of MOS transistors. In memory cells, a pronounced xe2x80x9csmilingxe2x80x9d effect of ONO dielectric impairs gate coupling ratio, gate channel control, and program, erase, and read efficiency.
A further drawback of the high doping is that it leads to a larger polysilicon grain size which in turn leads to a more rugged interface between the gate oxide and the polysilicon gate in MOS transistors, and similarly between each of the tunnel oxide and the floating gate, bottom of the ONO dielectric and the floating gate, and top of the ONO dielectric and the control gate in a memory cell. In extreme cases, it may lead to gate oxide and/or tunnel oxide pinch-off or otherwise impact the integrity and reliability characteristics of the gate oxide in MOS transistors and the tunnel oxide and the ONO dielectric in memory cells.
In conventional processes, the room to achieve the necessary trade-off between the desirable and undesirable effects of the polysilicon doping is limited to only regulating the level of doping and uniformity of the doping profile across the polysilicon layers. Achieving the desired trade off thus often proves to be a difficult task from process and device optimization point of view.
Accordingly, there is a need for polysilicon layers structure and method of forming the same whereby an optimum polysilicon doping profile can be achieved, the depletion of the polysilicon and its associated adverse effects are prevented or minimized, the quality and uniformity of the polysilicon-oxide interface are improved, while the xe2x80x9csmilingxe2x80x9d effect in the dielectric layers interfacing polysilicon is minimized.
In accordance with an embodiment of the present invention, a doped polysilicon layer interfaces a dielectric layer through an undoped polysilicon layer. In this manner, the drawbacks of the prior art structures wherein the doped polysilicon layer is in direct contact with the insulating layer are minimized or eliminated, while the advantages of a doped polysilicon layer is maintained.
In one embodiment, a semiconductor structure includes an undoped polysilicon layer, a doped polysilicon layer in contact with the undoped polysilicon layer, and an insulating layer in contact with the undoped polysilicon layer. The undoped polysilicon layer is sandwiched between the doped polysilicon layer and the insulating layer.
In accordance with an embodiment of the present invention, a semiconductor non-volatile memory cell includes a first insulating layer over a substrate region. A floating gate includes a first polysilicon layer over the first insulating layer and a second polysilicon layer over and in contact with the first polysilicon layer. The first polysilicon layer has a predetermined doping concentration and the second polysilicon layer has a doping concentration which decreases in a direction away from an interface between the first and second polysilicon layers. A second insulating layer overlies and is in contact with the second polysilicon layer. A control gate includes a third polysilicon layer over and in contact with the second insulating layer, and a fourth polysilicon layer over and in contact with the third polysilicon layer. The fourth polysilicon layer has a predetermined doping concentration, and the third polysilicon layer has a doping concentration which decreases in a direction away from an interface between the third and fourth polysilicon layers.
In another embodiment, the floating gate further includes a fifth polysilicon layer over and in contact with the first insulating layer. The first polysilicon layer overlies and is in contact with the fifth polysilicon layer. The fifth polysilicon layer having a doping concentration which decreases in a direction away from an interface between the first and fifth polysilicon layers.